The substantial advances in integrated circuit technology have resulted in large scale integration (LSI) and very large scale integration (VLSI) circuit structures wherein literally hundreds of logic devices are placed on a single silicon chip. However, such high levels of integration present substantial problems in debugging and testing of these integrated circuits. Due to the nature of the highly integrated circuitry, internal nodes cannot be directly accessed and therefore specific internal circuitry cannot be directly tested. Such circuits therefore can generally only be tested by transmitting and receiving signals through external input/output (I/O) terminals of the circuit.
In an attempt to overcome this problem, the use of set/scan registers has been suggested wherein the internal storage elements (e.g., latches) in the integrated circuit are configured so that they can be selectively controlled to operate as shift registers for test purposes. For testing, some of the shift register stages are configured to provide inputs to the combinational logic network to be tested while other shift register stages are configured to accept and store outputs from the combinational logic network in response to the applied test patterns. These outputs are later shifted through the shift register chain to external apparatus for analyzing the test results. The following documents generally relate to the development of set/scan registers and are hereby incorporated by reference: (1) Eichelberger et al, "A Logic Design Structure for LSI Testability", Proc. 14th Design Automation Conference, New Orleans, June 20-22, (1977) pp. 462-468; (2) U.S. patent application Ser. No. 694,931 now U.S. Pat. No. 4,697,279 entitled "Test/Master/Slave Triple Latch Flip-Flop" by Baratti et al, filed 11/4/85 which is assigned to the assignee of the present invention; and (3) Craig et al, "Pseudo-Exhaustive Adjacency Testing: a BIST Approach for Stuck-Open Faults", International Test Conference, November (1985).
CMOS is rapidly becoming a dominant logic technology for VLSI circuits. One of the testing challenges for CMOS circuit implementation is the detection of stuck-open faults which have been shown to cause combinational circuits to exhibit sequential behavior. The most common approach for testing for stuck-open faults employs a two-pattern test. The first pattern is generally referred to as an initialization test pattern and it is used to drive the output of the devices or gates under test to a given logic state. The second test pattern is generally referred to as a detection test pattern and it is used to activate one path to VDD or ground through the devices under test. If the device under test is stuck open, the device will exhibit a memory property and the output of the device will remain at the value stored during the initialization test pattern. On the other hand, if the device is operating properly it will change state.
It has recently been shown that the two-pattern test must be chosen carefully so that the tests are not invalidated by time-skews in input variable changes or unequal path delays. The invalidation generally occurs when certain function hazards in the faulty circuit or static hazards are excited during the transition from the initialization test pattern to the detection test pattern. Such hazards tend to momentarily close a spurious path to ground in parallel with the device under test and potentially cause the appearance of correct behavior when the device actually has a stuck-open fault. Invalidation of the test results can also potentially occur if a path is closed to a large isolated capacitance, appropriately charged or discharged, within a complex gate. In gates with drive transmission gates, it is also possible for a charge node to extend outside of the gate under test.